Xpedion Design Systems, Inc. and Cadence Design Systems, Inc. (NYSE:CDN) today announced the integration of the Xpedion GoldenGate(TM) family of radio frequency simulation and modeling products with the Cadence(R) Signal Processing Worksystem (SPW) and Cadence Analog Design Environment. The new product integration provides the designers of 3G, Bluetooth and RF integrated circuits (RF IC) with a unified bottom-up and top-down design methodology.
"This integration provides an automatic way to bring very accurate, high-performance, parametric models into the SPW and Analog Design Environment," said Les Wilson, director of marketing at Cadence. Xpedion's GoldenGate/Neural Network Model Compiler(TM) (NN-Model Compiler) accepts input data from the Analog Design Environment or from lab-measured data, and generates fully parametric SPW simulation models automatically. This gives users a rapid way of developing complex models in a bottom-up design flow. The integration of GoldenGate/Sim(TM) within the Analog Design Environment provides users with multi-tone and complex 3G modulation analysis capability to rapidly check those models in a top-down flow. Together the products augment Analog Design Environment's existing RF and wireless capabilities.
"Cadence's Analog Design Environment and Spectre(R) RF have been widely adopted in the RF IC design community," said Ed Lechner, director of product marketing for analog, mixed-signal and RF solutions at Cadence. "The combination of Xpedion's GoldenGate family and Cadence's proven RF and wireless solution provides our customers with the most comprehensive range of advanced simulation and analysis capabilities all tightly integrated into the Analog Design Environment."
Combining the power of GoldenGate with SPW empowers designers to make critical design trade-offs at both the circuit and system level, throughout the wireless communication system development cycle. From the bottom-up flow, the RF design team can simulate at the circuit level with GoldenGate/Sim, using modulated signal data from SPW running system-level streams. For a top-down flow, the system-level architects performing SPW simulation can directly import the RF blocks in C-language form generated by the Xpedion GoldenGate NN-Model Compiler. The interface also supports the ability to drive Xpedion's model compiler with direct simulation results from Cadence's Spectre(R) circuit simulator.
"This integration is another powerful tool for communication system architects and RF circuit designers," said Richard Curtin, senior vice president of sales and marketing at Xpedion. "The interface gives users of SPW and Analog Design Environment access to flexible top-down and bottom-up development flows in order to keep pace with the time-to-market and complexity of today's evolving wireless standards."
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